1. Field of the Invention
The present invention relates generally to integrated circuits which include a microprocessor coupled to an instruction cache, and more particularly, to testing of such integrated circuits.
2. Description of the Related Art
High speed microprocessors typically are used in conjunction with an instruction cache. Instructions stored by an instruction cache can be retrieved by the microprocessor far more rapidly than can instructions stored by other memory storage means such as by a main memory unit. In order to most efficiently utilize an instruction cache, the instructions stored by the cache usually include the instructions which are likely to be most frequently executed by the microprocessor. The instruction cache, therefore, enhances the speed of operation of the microprocessor by providing to the microprocessor relatively rapid access to the most frequently executed instructions.
Recently, circuits have been produced which include both a microprocessor and an instruction cache on a single integrated circuit. In these circuits, the instruction cache essentially forms a part of the instruction pipeline which communicates with the microprocessor.
While integrated circuits comprising both a microprocessor and an instruction cache generally have been successful, there have been shortcomings with their use. More particularly, testing of the integrity of an instruction cache included within such a circuit often has been quite burdensome.
Testing of an instruction cache ordinarily involves testing the integrity of the cache with regard to storage of a variety of instructions and combinations of instructions. Each memory location of the cache is tested in order to determine whether it can store digital electronic signals at both logical 1 signal levels and logical 0 signal levels.
In the past, testing of the instruction cache of an integrated circuit comprising both such a cache and a microprocessor has been difficult because the cache essentially formed a part of the instruction pipeline which fed instructions to the microprocessor. Consequently, instructions retrieved from the instruction cache generally were provided directly to the microprocessor for execution.
One earlier method for testing the instruction cache involved initially storing instructions in the cache, and subsequently, retrieving those instructions from the cache for execution by the microprocessor. The results of execution by the microprocessor then were observed, and inferences could be drawn regarding the integrity of the instruction cache based upon the performance of the microprocessor in executing the instructions. Unfortunately, this method of testing often was not satisfactory because it could be difficult to draw accurate conclusions about the integrity of the instruction cache based upon the results of processing by the microprocessor.
An alternative earlier method involved decoupling the instruction cache from the microprocessor and conducting test signals between the cache and an external testing apparatus. Using this alternative method of testing, the integrity of memory locations of the cache could be tested without the need for execution of instructions by the microprocessor. Accordingly, testing using the alternative method involved merely providing bit combinations to the instruction cache, temporarily storing the provided bits, retrieving the stored bits and observing whether or not any of the stored bits had been corrupted during storage.
The alternative method eliminated the need to draw inferences about the integrity of the instruction cache based upon the results of the processing of stored instructions by the microprocessor. Furthermore, it eliminated the need to perform testing using only combinations of bits representing instructions; since the alternative method did not require the actual execution of instructions by the microprocessor. Therefore, at least to some extent, the alternative method was an improvement over the earlier method first discussed.
The alternative method, however, could be difficult to implement because it involved decoupling of the instruction cache from the microprocessor. More specifically, implementation of the alternative method required the use of an apparatus to decouple the cache from the microprocessor and to control the communication of signals to and from the instruction cache independent of the operation of the microprocessor.
Thus, there has existed a need for an improved integrated circuit comprising a microprocessor coupled to an instruction cache in which the integrity of the instruction cache can be more easily tested and for an improved method for testing the instruction cache. The present invention meets these needs.